1. Field of the Invention
The invention relates to semiconductor devices and methods of making the same, and more particularly relates to such devices and methods in which FinFET structures are formed on a semiconductor substrate.
2. Description of Related Art
As the gate length of transistors continues to decrease with successive generations of semiconductor devices, new transistor configurations have been needed to counteract the diminished response that would otherwise occur with shrinking gate lengths. One such design configuration is referred to variously as a FinFET or tri-gate transistor, in which the source, drain and channel region of each transistor is elevated relative to a semiconductor substrate. The elevated portion has the shape of a ridge or fin, and may be formed integrally with the underlying substrate or may be formed on an insulating layer in the case of SOI type devices. The gate wraps around the three projecting sides of the fin, and so the available channel area is increased by the gate contacting not only the top part of the fin but also its side walls.
It is also known to provide different materials for the channel region of nFET transistors relative to pFET transistors. For example, silicon-germanium (SiGe) as a channel material enhances performance of pFET transistors relative to silicon, but the same is not the case for nFET transistors. Therefore, FinFETS have been proposed in which the channel of the pFET transistors is formed from SiGe, whereas the channel of the nFET transistors is made of silicon.
U.S. Pat. No. 7,198,990 discloses forming FinFETS on a silicon-on-insulator (SOI) substrate by etching the upper layer of silicon to make Si fins, masking the Si fins of the nFET transistors, and depositing a layer of SiGe on the fins of the pFET transistors. However, with this technique, the width of the fins of each channel type is difficult to control relative to the other channel type, and may vary significantly.
U.S. Pat. No. 7,842,559 discloses forming FinFETS by forming a trench for silicon channels to expose an underlying silicon substrate, and after forming an Si fin in that trench, forming a further trench to expose a SiGe film that overlies the silicon substrate, and then forming a SiGe fin in that further trench. However, with this technique, impurity doping is needed for the fin regions intersecting the SiGe layer, to prevent punch-through leakage current.